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3-1 tm file number 4105.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 HI2302 8-bit, 50 msps, video a/d converter with clamp function the HI2302 is an 8-bit cmos a/d converter for video with synchronizing clamp function. the adoption of two-step parallel method achieves low power consumption and a maximum conversion rate of 50 msps. for pin compatible lower sample rate converters refer to hi1179 (35 msps) or hi1176 (20 msps) data sheets. applications video digitizing wireless receivers lcd projectors/panels cable modems rgb graphics processing camcorders instrumentation features resolution . . . . . . . . . . . . . . . . . . . . 8-bit 0.5 lsb (dnl) maximum sampling frequency . . . . . . . . . . . . . 50 msps low power consumption . . . . . . . . . . . . . . . . . . . .125mw (reference current excluded) built-in input clamp function (dc restore) clamp on/off function internal voltage reference input cmos/ttl compatible three-state ttl compatible output power supply . . . . . . . . . . . . . . . . . . . . . . . . . . +5v single or +5v/3.3v dual direct replacement for sony cxd2302q pinout HI2302 (mqfp) top view ordering information part number temp. range ( o c) package pkg. no. HI2302jcq -40 to 85 32 ld mqfp q32.7x7-s av dd clp nc nc clk test dv dd test v rbs v ref ccp dv ss cle oe dv ss nc d0 d1 d2 d3 d4 d5 d6 d7 v rb av ss av ss v in av dd av dd v rt v rts 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 data sheet november 1997
3-2 functional block diagram + - lower sampling comparator (4-bit) lower sampling comparator (4-bit) upper sampling comparator (4-bit) lower encoder (4-bit) lower encoder (4-bit) upper encoder (4-bit) lower data latch upper data latch clock generator 30 31 2 3 4 5 6 7 8 10 11 12 reference supply 29 27 26 d-ff 28 25 24 23 22 21 20 19 18 17 16 15 14 13 v rts av dd v rt av dd v in av ss av ss v rb v rbs av dd clp nc nc v ref ccp cle 9 32 nc test (open) clk test (open) dv dd d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) dv ss oe dv ss 1 HI2302
3-3 absolute maximum ratings t a =25 o c thermal information supply voltage (v dd ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7v reference voltage (v rt , v rb ) . . . . . . . . . . . .v dd +0.5 to v ss -0.5v input voltage (analog) (v in ) . . . . . . . . . . . . .v dd +0.5 to v ss -0.5v input voltage (digital) (v i ) . . . . . . . . . . . . . . .v dd +0.5 to v ss -0.5v output voltage (digital) (v o ) . . . . . . . . . . . . .v dd +0.5 to v ss -0.5v operating conditions supply voltage (av dd , av ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 to 5.25v (dv dd , dv ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5v (dv ss -av ss ? ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 100mv reference input voltage (v rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 and above v (v rt ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7 and below v analog input (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . 1.7v p-p above clock pulse width (t pw1 , t pw0 ) . . . . . . . . . . . . . . . . . . . 10ns (min) ambient temperature (t opr ) . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -55 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (mqfp - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations f c = 50 msps, av dd = 5v, dv dd = 3 to 5.5v, v rb = 0.5v, v rt = 2.5v, t a = 25 o c parameter symbol test conditions notes min typ max units analog characteristics maximum conversion rate f c max av dd = 4.75 to 5.25v, t a =20to75 o c, v in = 0.5 to 2.5v, f in = 1khz triangular wave 50 65 - msps minimum conversion rate f c min - - 0.5 msps input bandwidth full scale bw envelope r in = 33 ? -1db - 60 - mhz -3db - 100 - mhz differential nonlinearity error e d end point - 0.3 0.5 lsb integral nonlinearity error e l - +0.7 1.5 lsb offset voltage e ot potential difference to v rt note 2 -70 -50 -30 mv e ob potential difference to v rb 20 40 60 mv differential gain error dg ntsc 40 ire mod ramp f c = 14.3 msps -3- % differential phase error dp - 1.5 - deg rees sampling delay t sd -0- ns clamp offset voltage e oc v in = dc, c in = 10 f t pcw = 2.75 s, f c = 14.3 msps, f clp = 15.75khz v ref = 0.5v 0 20 40 mv v ref = 2.5v 0 20 40 mv signal-to-noise ratio snr f in = 100khz - 45 - db f in = 500khz - 44 - db f in = 1mhz - 44 - db f in = 3mhz - 43 - db f in = 10mhz - 38 - db f in = 25mhz - 32 - db spurious free dynamic sfdr f in = 100khz - 51 - db f in = 500khz - 46 - db f in = 1mhz - 49 - db f in = 3mhz - 46 - db f in = 10mhz - 45 - db f in = 25mhz - 45 - db HI2302
3-4 dc characteristics f c = 50 msps, av dd = 5v, dv dd = 5v or 3.3v, v rb = 0.5v, v rt = 2.5v, t a = 25 o c supply current i ad + i dd ntsc ramp, wave input, cle = 0v dv dd = 5v - 25 36 ma analog i ad dv dd = 3.3v - 23 33 ma digital i dd -23ma reference current i ref 4.1 5.4 7.7 ma reference resistance (v rt - v rb ) r ref 260 370 480 ? self-bias voltage v rb shorts v rts and a vdd shorts v rbs and a vss 0.52 0.56 0.60 v v rt - v rb 1.80 1.92 2.04 v input capacitance c ai1 v in , v in = 1.5v + 0.07v rms -15- pf c ai2 v rts , v rt , v rb , v rbs , v ref - - 11 pf c din test, clk, clp, cle, oe - - 11 pf output capacitance c ao ccp - - 11 pf c do d0 to d7, test - - 11 pf digital input voltage v ih av dd = 4.75 to 5.25v, dv dd = 3 to 5.5v, t a = -20 o c to 75 o c 2.2 - - v v il - - 0.8 v digital input current i ih i il v i = 0v to av dd , t a = 20 o c to 75 o c clk -240 - 240 a test, clp, cle -240 - 40 a oe -40 - 240 a digital output current i oh oe = 0v, dv dd = 5v t a = 20 o c to 75 o c v oh = dv dd - 0.8v - - -2 ma i ol v ol = 0.4v 4 - - ma i oh oe = 0v dv dd = 3.3v t a = -20 o c to 75 o c v oh = dv dd - 0.8v - - -1.2 ma i ol v ol = 0.4v 2.4 - - ma i ozh oe = 3v dv dd = 3 to 5.5v t a = -20 o c to 75 o c v oh = dv dd -40 - 40 a i ozl v ol = 0v -40 - 40 a timing f c = 50 msps, av dd = 5v, dv dd = 5v or 3.3v, v rb = 0.5v, v rt = 2.5v, t a = 25 o c output data delay t pzh cl = 15pf oe = 0v dv dd = 5v 5.5 9.5 12.0 ns t phl 8.5 ns t plh dv dd = 3.3v 4.3 11.8 16.3 ns t phl 7.6 ns three-state output enable time t pzh r l = 1k ? c l = 15pf oe = 3v ? 0v dv dd = 5v 2.5 4.5 8.0 ns t pzl 6.0 ns t pzh dv dd = 3.3v 3.0 7.0 9.0 ns t pzl 5.0 ns three-state output enable time t phz , t plz r l = 1k ? , c l = 15pf oe = 3v ? 0v dv dd = 5v 3.5 5.5 7.5 ns t pzh ,t pzl dv dd = 3.3v 2.5 5.5 8.0 ns clamp pulse width t cpw f c = 14.3mhz, c in = 10 f for ntsc wave note 4 1.75 2.75 3.75 s notes: 2. the offset voltage e ob is a potential difference between v rb and a point of position where the voltage drops equivalent to 1 / 2 lsb of the voltage when the output data changes from ?0000000?to ?0000001? e ot is a potential difference between v rt and a potential point where the voltage rises equivalent to 1 / 2 lsb of the voltage when the output data changes from ?1111111?to ?1111110? 3. the voltage of up to (av dd + 0.5v) can be input when dv dd = 3.3v. but the output pin voltage is less than the dv dd voltage. when the digital output is in the high impedance mode, the ic may be damaged by applying the voltage which is more than the (dv dd + 0.5v) voltage to the digital output. 4. the clamp pulse width is for ntsc as an example. adjust the rate to the clamp pulse cycle (1/15.75khz for ntsc) for other processing systems to equal the values for ntsc. electrical speci?ations f c = 50 msps, av dd = 5v, dv dd = 3 to 5.5v, v rb = 0.5v, v rt = 2.5v, t a = 25 o c (continued) parameter symbol test conditions notes min typ max units HI2302
3-5 timing diagrams figure 1a. timing chart figure 1b. timing chart figure 1c. timing chart = analog signal sampling point n + 1 n + 4 n + 3 n n - 1 n + 2 n + 1 n - 2 n - 3 n t pw1 t pw0 clock 1.3v analog input data output t r 4ns t f 4ns 1.3v 0.7 dv dd 0.3 dv dd data output t plh, t phl clock 90% 10% 3v 0v t r = 4.5ns t f = 4.5ns oe input output 1 output 2 1.3v t plz 10% 90% t phz t pzh 1.3v 1.3v t pzl 10% 90% 3v 0v v oh v ol ( dv ss ) v oh ( dv dd ) v ol HI2302
3-6 figure 1d. timing chart ii timing diagrams (continued) vi (1) vi (2) vi (3) vi (4) (1) (2) (3) (4) s (1) c (1) s (2) c (2) s (3) c (3) s (4) c (4) md (0) md (1) md (2) md (3) rv (0) rv (1) rv (2) rv (3) s (1) h (1) c (1) s (3) h (3) c (3) ld (-1) ld (1) analog input external clock upper comparators block upper data lower reference voltage lower comparators a block lower data a lower comparators b block lower data b digital output h (0) c (0) s (2) h (2) c (2) s (4) h (4) ld (-2) ld (0) ld (2) out (-2) out (-1) out (0) out (1) pin descriptions pin no. symbol equivalent circuit description 1 to 8 d0 to d7 d0 (lsb) to d7 (msb) output. di dv dd dv ss HI2302
3-7 9 test leave open for normal use. 10 dv dd digital power supply +5v or +3.3v. 11 test leave open for normal use. pull-up resistor is built in. 15 clp input for the clamp pulse. clamps the signal voltage during low interval. pull-up resistor is built in. 29 cle the clamp function is enabled when cle = low. the clamp function is off and the device functions as a normal a/d converter when cle = high. pull-up resistor is built in. 12 clk clock input. set to low level when no clock is input. 13, 14, 32 nc 16, 19, 20 av dd analog power supply +5v. 17 v rts generates approximately +2.5v when shorted with av dd . 18 v rt reference voltage (top). 24 v rb reference voltage (bottom). 25 v rbs generates approximately +0.6v when shorted with av ss . 21 v in analog input. pin descriptions (continued) pin no. symbol equivalent circuit description 9 dv dd dv ss 11 15 29 av ss av dd 12 av dd av ss 17 18 25 24 av dd av ss r t rb r ref 21 av dd av ss HI2302
3-8 digital output the following table shows the relationship between analog input voltage and digital output code. 22, 23 av ss analog ground. 26 v ref clamp reference voltage input. clamps so that the reference voltage and the input signal during clamp interval are equal. 27 ccp integrates the clamp control voltage. the relationship between the changes in ccp voltage and in v in voltage is positive phase. 28, 31 dv ss digital ground. 30 oe data is output when oe = low. pins d0 to d7 are at high impedance when oe = high. pull-down resistor is built in. input signal voltage step digital output code msb lsb v rt 0 11111111 127 10000000 128 01111111 v rb 255 00000000 pin descriptions (continued) pin no. symbol equivalent circuit description 26 av dd av ss 27 av dd av ss 30 av dd av ss HI2302
3-9 electrical speci?ations measurement circuits note: c l includes capacitance of probes. figure 2. output data delay measurement circuit figure 3. three-state output measurement circuit figure 4. integral nonlinearity error/differential nonlinearity error/offset voltage test circuit figure 5. differential gain error, differential phase error test circuit measurement point to output pin c l measurement dv dd to output pin c l r l point r l buffer a < b a > b comparator . . . a8 a1 a0 . . . b8 b1 b0 +v dut HI2302 + - -v dvm controller to .. . 000 00 .. . 111 10 8 ? 8 ? 8 v in clk (50 msps) s1 s2 s1: on if a < b s2: on if b > a ntsc signal source HI2302 ttl ecl 10-bit d/a vector scope 100 40 ire iae 0 -40 modulation burst sync f c s.g. (cw) ttl ecl v in 8 8 hi20201 620 -5.2v clk -5.2v 620 d.g. d.p. 0.5v 2.5v HI2302
3-10 operation (see block diagram and timing chart ii) the HI2302 is a two-step parallel system a/d converter featuring a 4-bit upper comparator block and two lower comparator blocks of 4-bit each. the reference voltage that is equal to the voltage between v rt - v rb /16 is constantly applied to the upper 4-bit comparator block. voltage that corresponded to the upper data is fed through the reference supply to the lower 4-bit comparator block. voltage that corresponded to the upper data is fed through the reference supply to the lower 4-bit comparator block. v rts and v rbs pins serve for the self generation of v rt (reference voltage top) and v rb (reference voltage bottom), and they are also used as the sense pins as shown in the application circuit examples figures 10 and 11. this ic uses an offset cancel type comparator which operates synchronously with an external clock. it features the following operating modes which are respectively indicated on the timing chart ii with s, h, c symbols. that is input sampling (auto zero) mode, input hold mode and comparison mode. the operation of respective parts is as indicated in the timing chart ii. for instance, input voltage vi (1) is sampled with the falling edge of the external clock (1) by means of the upper comparator block and the lower comparator a block. the upper comparator block ?alizes comparison data md (1) with the rising edge of the external clock (2). simultaneously the reference supply generates the lower reference voltage rv (1) that corresponded to the upper results. the lower comparator a block ?alizes comparison data ld (1) with the rising edge of the external clock (3). md (1) and ld (1) are combined and output as out (1) with the rising edge of the external clock (4). accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. notes on operation ? dd ,v ss to reduce noise effects, separate the analog and digital systems close to the device. for both the digital and analog v dd pins, use a ceramic capacitor of about 0.1 f set as close as possible to the pin to bypass to the respective gnds. analog input compared with the ?sh type a/d converter, the input capacitance of the analog input is rather small. however, it is necessary to conduct the drive with an ampli?r featuring suf?ient band and drive capability. when driving with an ampli?r of low output impedance, parasitic oscillation may occur. that may be prevented by insetting a resistance of about 33 ? in series between the ampli?r output and a/d input. when the v in signal of pin no. 21 is monitored, the kickback noise of clock is. however, this has no effect on the characteristics of a/d conversion. clock input the clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. reference input voltage v rt to v rb is compatible with the dynamic range of the analog input. bypassing v rt and v rb pins to gnd, by means of a capacitor about 0.1 f, stable characteristics are obtained. by shorting v dd and v rts , v ss and v rbs respectively, the self-bias function that generates v rt = about 2.5v and v rb = about 0.6v, is activated. timing analog input is sampled with the falling edge of clk and output as digital data synchronized with a delay of 2.5 clocks and with the following rising edge. the delay from the clock rising edge to the data output is about 9ns (dv dd = 5v). oe pin pins 1 to 8 (d 0 to d 7 ) are in the output mode by leaving oe open or connecting it to dv ss , and they are in the high impedance mode by connecting it to dv dd . figure 6. digital output current test circuit electrical speci?ations measurement circuits (continued) 2.5v 0.5v v ol i ol + - v rt v in v rb v dd clk oe gnd 2.5v 0.5v v oh ioh + - v rt v in v rb v dd clk oe gnd HI2302
3-11 application circuits figure 7. single +5v power supply when clamp is used (self-bias used) notes: 5. the relationship between the changes in ccp voltage (pin 27) and in v in voltage is positive phase. 6. ? v in / ? v ccp = 3.0 (f s = 20 msps). figure 8. single +5v power supply digital clamp (self-bias used) 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 + aco4 0.01 gnd (analog) 10 33 ? video in clock in gnd (digital) 0.01 20k v ref +5v (analog) +5v (analog) 0.01 0.1 10p clamp pulse in +5v (digital) 0.1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 open 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 aco4 +5v (digital) 0.1 0.01 +5v (analog) 10 33 ? 10p video in + 0.01 0.1 dac gnd (digital) clock in clamp level pwm etc. ? ? subtracter comparator etc. ? ? setting data information other than that for clamp interval is at high impedance open gnd (analog) HI2302
3-12 figure 9. single +5v power supply when clamp is not used (self-bias used) figure 10. when clamp is used (self-bias not used) application circuits (continued) 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 d7 d6 d5 d4 d3 d2 d1 d0 aco4 0.01 clock in +5v (analog) 0.1 33 ? 10p video in 0.01 gnd (analog) gnd (digital) +5v (digital) 0.1 open 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 + - + - aco4 clock in clamp pulse in v rt video in v rb 0.01 +5v (analog) 10 33 ? 0.1 10p 0.01 +5v (analog) v ref 20k +5v (digital) 0.1 open d7 d6 d5 d4 d3 d2 d1 d0 gnd (digital) 0.01 gnd (analog) HI2302
3-13 figure 11. single +5v power supply when clamp is not used (self-bias not used) figure 12. dual +5v/+3.3v power supply when clamp is used (self-bias used) application circuits (continued) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 d7 d6 d5 d4 d3 d2 d1 d0 +5v (digital) 0.1 open gnd (digital) gnd (analog) + - + - clock in v rt video in v rb aco4 0.01 +5v (analog) 33 ? 0.1 10p 0.01 17 18 19 20 21 22 23 24 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 8 7 6 5 4 3 2 1 clock in clamp pulse in video in aco4 +5v (analog) +5v (analog) 0.01 10 0.1 0.01 10p 0.01 33 ? v ref 20k gnd (analog) open 0.1 +3.3v (digital) d7 d6 d5 d4 d3 d2 d1 d0 + gnd digital HI2302
3-14 typical performance curves figure 13. ambient temperature vs supply current figure 14. supply voltage vs supply current figure 15. sampling frequency vs supply current figure 16. input frequency vs supply current figure 17. ambient temperature vs maximum operating frequency figure 18. supply voltage vs maximum operating frequency 26 25 24 -200 255075 ambient temperature ( o c) f c = 50 msps ntsc ramp wave input av dd = dv dd = 5v supply voltage (ma) 27 25 23 supply current (ma) 4.75 5 5.25 supply voltage (v) f c = 50 msps ntsc ramp wave input av dd = dv dd t a = 25 o c 25 20 15 10 20 30 40 50 sampling frequency (msps) supply current (ma) ntsc ramp wave input av dd = dv dd = 5v t a = 25 o c 35 30 25 0.01 0.1 1 10 25 supply current (ma) input frequency (mhz) f c = 50 msps sine wave 1.9v p-p av dd = dv dd = 5v t a = 25 o c 70 65 60 ambient temperature ( o c) -20 0 25 50 75 maximum operating rate (msps) f c = 50 msps f in = 1khz, triangular wave input av dd = dv dd = 5v 63 65 67 maximum operating rate (msps) 4.75 5 5.25 supply voltage (v) f c = 50 msps ntsc ramp wave input av dd = dv dd HI2302
3-15 figure 19. ambient temperature vs sampling delay figure 20. full scale input bandwidth figure 21. analog input frequency vs snr, effective number of bits (enob) figure 22. analog input frequency vs sfdr figure 23. ambient temperature vs output data delay figure 24. ambient temperature vs output data delay typical performance curves (continued) 1 0 -1 sampling delay (ns) -200 255075 ambient temperature ( o c) f c = 50 msps av dd = dv dd = 5v 0 -1 -3 0.1 1 10 100 analog input frequency (mhz) output level (db) f c = 50 msps sine wave 1v p-p input av dd = dv dd = 5v t a = 25 o c 50 40 30 snr (db) 8 7 6 10 1 analog input frequency (mhz) 0.1 0.01 5 enob f c = 50 msps av dd = dv dd = 5v v in = 2v p-p t a = 25 o c 60 50 40 30 0.01 0.1 1 10 analog input frequency (mhz) sfdr (db) f c = 50 msps av dd = dv dd = 5v v in = 2v p-p t a = 25 o c 6 8 10 12 output data delay (ns) t plh t phl -20 0 25 50 75 ambient temperature ( o c) f c = 10 msps av dd = dv dd = 5v c l = 15pf 6 8 10 12 output data delay (ns) t plh t phl -20 0 25 50 75 ambient temperature ( o c) f c = 10 msps av dd = 5v dv dd = 3.3v c l = 15pf HI2302
3-16 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com figure 25. load capacitance vs output data delay figure 26. load capacitance vs output data delay figure 27. dv dd supply voltage vs output data delay typical performance curves (continued) 6 8 10 12 t plh t phl 0 output data delay (ns) 510152025 load capacitance (pf) f c = 10 msps av dd = dv dd = 5v t a = 25 o c 14 12 10 8 6 output data delay (ns) 0 5 10 15 20 25 t plh t phl f c = 10 msps av dd = 5v dv dd = 3.3v t a = 25 o c load capacitance (pf) 12 10 8 6 3 3.5 4.5 5 5.5 t plh output data delay (ns) dv dd supply voltage (v) t phl f c = 10 msps av dd = 5v c l = pf t a = 25 o c HI2302

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